Advanced JTAG Emulators by Blackhawk

JTAG
 
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Products

Advanced JTAG Emulators

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XDS560-class

USB560-BP JTAG Emulator

USB560m JTAG Emulator

LAN560 JTAG Emulator

PCI560 JTAG Emulator

XDS510-class

USB510 JTAG Emulator

USB510L JTAG Emulator

USB2000 Controller

XDS100-class

USB100v1 Controller

USB100v2 Controller

USB100v2 Controller (model D)

XDS560 Trace

XDS560 Trace System

Special Hardware

GANG2000 Programmer

Adapters

Pin Converters

Isolation Adapter

JTAG Adaptive Clocking Kit for OMAP™

Software

Boundary Scan

JTAG Circuit Board Test Tools

In-System Programming

Utilities

BHCheck33, BHDetect, BHLoader, BHProbe

Applications

BHFlashburn, Remote Emulation Server

Operating Systems and APIs

TALON RTOS

Tailwind POSIX API

Services

Hardware Development

Software Development

Consulting

Embedded Emulation Solutions

 

 

Blackhawk JTAG Emulators for Texas Instruments (TI) DSPs are Advanced, High-speed USB, PCI and LAN based products. Blackhawk Emulators support a wide array of Texas Instruments devices which include TMS320™ C5000™ Low Power DSPs, C6000™ High Performance DSPs, StellarisĀ® ARMĀ® Cortex™-based MCUs, Delfino™ and Piccolo™ C2000™ 32-bit Real-time MCUs, TMS470 (ARM®), OMAP™ Applications Processors, Sitara ARM Cortex™ A8 and ARM9, and DaVinci™ Video Processor platforms. Blackhawk JTAG emulators are compatible with Code Composer Studio (CCStudio™)IDE software. Blackhawk JTAG Emulators are available from a worldwide network of industry resellers and distributors. Blackhawk XDS560-class JTAG emulators now support the Corelis JTAG Boundary Scan tools. Corelis and Blackhawk are both part of EWA Technologies, Inc. and have integrated the powerful boundary-scan tools from Corelis with the advanced JTAG emulator from Blackhawk.  This integration allows customers who are currently using a Blackhawk JTAG Emulator to debug their TI DSP boards and extend their test capability by being able to run Corelis JTAG Boundary Scan software tools without the added expense of  purchasing another controller.  Increased capabilities for testing and debugging without the added cost of dedicated hardware. 


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JTAG

The term JTAG is an acronym for Joint Test Action Group, a consortium of companies that banded together in 1985. The purpose was to devise a method of testing hardware at the IC level in an effort to eliminate the time consuming and costly procedure of building test fixtures. Their efforts resulted in a specification published by the IEEE as 1149.1. Today, IEEE 1149.1 is commonly referred to and interchangeable with "boundary scan". While the terms JTAG and boundary scan may be thought of as identical, there are major differences in the implementation based on the manufacturer and specific hardware design models. There are however, a few basic elements that must be present to facilitate JTAG functionality.


Additional Resources

Texas Instruments Wiki on JTAG...........................................[goto TI WiKi
Comprehensive Online JTAG Tutorial.....................................[goto Corelis
Emulation Fundamentals for TI's DSP Solutions.......................[download pdf]
XDS Target Connection Guide TI Wiki....................................[goto TI WiKi]
Emulation and Trace Headers Technical Reference Manual.......[download pdf]
JTAG/IEEE 1149.1 Design Considerations...............................[download pdf]

Texas Instruments JTAG Emulator Configurations

At the present time, there are three JTAG emulator configurations that are in use on Texas Instruments Development Kits (DSK) and Evaluation Modules (EVM).


Standard 14-pin JTAG Emulator Header
This is the most common of TI JTAG emulator headers. It is a 2x7 header  withstandard 14-pin jtag emulator header 0x100” x0.100” pin spacing. The pin configuration of this header is as follows:

TMS Test mode select
TDI Test data input
TDO Test data output
TCK Test Clock
TRST Test Reset
EMU0 Emulation pin 0
EMU1 Emulation pin 1
PD(Vcc) Presence detect
TCK_RET Test clock return
GND Ground



Compact TI (cTI) 20-pin JTAG Emulator Header

cTI jtag emulator header
This is a new JTAG emulator header that uses a 2x10 header (P/N: casd) with 0x100” x0.100” pin spacing. The pin configuration of this header is as follows:


TMS Test mode select
TDI Test data input
TDIS Target Disconnect
TDO Test data output
TCK Test Clock
nTRST Test Reset
nSRST System Reset
EMU0 Emulation pin 1
EMU1 Emulation pin 2
EMU2 Emulation pin 3
EMU3 Emulation pin 4
EMU4 Emulation pin 5
PD(Vcc) Presence detect
TCK_RET Test clock return
GND Ground



XDS560T Trace 60-pin JTAG Emulator Header

60-pin XDS560 Trace HeaderThe XDS560T Trace header is a high-density connector for
connection of the Trace Module. This highly-specialized
connection is used with the Code Compose IDE v3.3 or higher.
You can find more information on the Blackhawk XDS560T
module at this link.



A detailed description of the XDS560T Trace Emulation Header can be found in the Texas Instruments Knowledge Base article at this link.